1. Field of the Invention
The present invention relates to a state machine, and in particular to a state machine circuit capable of adjusting state switching in an integrated circuit chip.
2. Description of the Related Art
Currently, synchronous circuits are usually used in integrated circuits (ICs) for controlling modules and components in the IC. However, the cost for manufacturing an IC rises significantly relative to advances in the semiconductor manufacturing processes. If states in state machines of an IC are not well-designed and state modifications are required, the cost for remanufacturing a well-designed IC is extremely high when the number of logic gates required for the modifications exceeds the number of spare cells in the IC.
FIG. 1A is a block diagram illustrating a conventional state machine circuit 100. The conventional state machine circuit 100 may comprise a logic circuit 110, a register 120, and an output circuit 130. The logic circuit 110 is configured to control the state machine circuit to switch between multiple states, wherein each state has a state value and a corresponding output value. The logic circuit 110 may further output a predicted state or also known as a next state Q+. The register 120, coupled to the logic circuit 110, is configured to store a current state value of the current state QC of the state machine circuit 100. The register 120 may output the predicted state as the current state QC after a clock period. The output circuit 130 may determine an output value OUT according to the current state from the register 120 and inputs of the state machine circuit 100, wherein the aforementioned output value OUT is the output value of the state machine circuit 100. When the states of the state machine circuit 100 are not well-designed, the state machine circuit 100 may possibly be required to control switching of the states according to other additional signals, so that the design of the logic circuit 110 and the output circuit 130 needs to be alternated.
FIG. 1B is a diagram illustrating state switching of the conventional state machine circuit 100. For description, there are only two states illustrated in FIG. 1B to explain the state switching of the conventional state machine circuit 100. For example, in the original state design of the conventional state machine circuit 100, given that an input of the input signal IN of the state machine circuit 100 is SA, when the input signal SA=1, the state machine circuit 100 may switch from a current state S10 to a predicted state S11. It should be noted that the input signal IN may comprise multiple inputs. When the state design of the state machine circuit 100 is not well-designed, another input such as SB of the input signal IN may be required for the state machine circuit 100 to control state switching. For example, the state machine circuit 100 may switch from a state S10 to a state S11 given SA=SB=1 after state machine modification. Additionally, the state machine circuit 100 may keep at the state S10 given SA=1 and SB=0 after state machine modification. The number of spare cells in the IC is usually not sufficient to support such state machine modifications. In other words, it is impossible to achieve the modifications of the two paths (i.e. SA=SB=1, and SA=1, SB=0) in the IC, and the state design of the state machine circuit 100 can be only alternated by remanufacturing the IC. In view of the above, there is a demand for a state machine circuit capable of adjusting erroneous state switching or inserting extra new states in addition to the original states of the state machine circuit, thereby correcting improper state designs of the IC.